M48Z512A Datasheet, PDF (1/17 Pages) STMicroelectronics – 4 Mbit 512Kb x8 ZEROPOWER SRAM

M48Z512A
M48Z512AY
4 Mbit (512Kb x8) ZEROPOWER^® SRAM
s INTEGRATED LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
s CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
s 10 YEARS of DATA RETENTION in the
ABSENCE of POWER
s AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s WRITE PROTECT VOLTAGES
(V_PFD = Power-fail Deselect Voltage):
– M48Z512A: 4.50V ≤ V_PFD ≤ 4.75V
– M48Z512AY: 4.20V ≤ V_PFD ≤ 4.50V
s BATTERY INTERNALLY ISOLATED UNTIL
POWER IS APPLIED
s PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 512K x 8 SRAMs
s SURFACE MOUNT CHIP SET PACKAGING
INCLUDES a 28-PIN SOIC and a 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED
SEPARATELY)
s SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY
s SNAPHAT^® HOUSING (BATTERY) IS
REPLACEABLE
Table 1. Signal Names
A0-A18
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
V_CC
Supply Voltage
V_SS
Ground
March 2000
32
1
PMDIP32 (PM)
Module
SNAPHAT (SH)
Battery
32
1
TSOP II 32
(10 x 20mm)
SOH28
Surface Mount Chip Set Solution (CS)
Figure 1. Logic Diagram
VCC
19
A0-A18
8
DQ0-DQ7
W
M48Z512A
M48Z512AY
E
G
VSS
AI02043
1/17