M48Z35_10 Datasheet, PDF (1/24 Pages) STMicroelectronics – 256 Kbit (32 Kbit x 8) ZEROPOWER® SRAM

M48Z35
M48Z35Y
256 Kbit (32 Kbit x 8) ZEROPOWER^® SRAM
Features
■ Integrated, ultra low power SRAM, power-fail
control circuit, and battery
■ READ cycle time equals WRITE cycle time
■ Automatic power-fail chip deselect and WRITE
protection
■ WRITE protect voltages:
(V_PFD = Power-fail deselect voltage)
– M48Z35: V_CC = 4.75 to 5.5 V
4.5 V ≤ V_PFD ≤ 4.75 V
– M48Z35Y: 4.5 to 5.5 V
4.2 V ≤ V_PFD ≤ 4.5 V
■ Self-contained battery in the CAPHAT^™ DIP
package
■ Packaging includes a 28-lead SOIC and
SNAPHAT^® top (to be ordered separately)
■ Pin and function compatible with JEDEC
standard 32 K x 8 SRAMs
■ SOIC package provides direct connection for a
SNAPHAT^® top which contains the battery
■ RoHS compliant
– Lead-free second level interconnect
28
1
PCDIP28 (PC)
battery CAPHAT™
SNAPHAT^® (SH)
battery
28
1
SOH28 (MH)
August 2010
Doc ID 2608 Rev 9
1/24
www.st.com
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