M48Z35_07 Datasheet, PDF (1/23 Pages) STMicroelectronics – 256Kbit (32Kbit x 8) ZEROPOWER SRAM

M48Z35
M48Z35Y
256Kbit (32Kbit x 8) ZEROPOWER^® SRAM
Features
■ Integrated, ultra low power SRAM, power-fail
control circuit, and battery
■ READ cycle time equals WRITE cycle time
■ Automatic power-fail chip deselect and WRITE
protection
■ WRITE protect voltages:
(V_PFD = Power-fail Deselect Voltage)
– M48Z35: V_CC = 4.75 to 5.5V
4.5V ≤ V_PFD ≤ 4.75V
– M48Z35Y: 4.5 to 5.5V
4.2v ≤ V_pfd ≤ 4.5v
■ Self-contained battery in the CAPHAT™ DIP
package
■ Packaging includes a 28-lead SOIC and
SNAPHAT^® top (to be ordered separately)
■ Pin and function compatible with JEDEC
standard 32K x 8 SRAMs
■ SOIC package provides direct connection for a
SNAPHAT top which contains the battery
■ RoHS compliant
– Lead-free second level interconnect
28
1
PCDIP28 (PC)
Battery CAPHAT
SNAPHAT (SH)
Battery
28
1
SOH28 (MH)
November 2007
Rev 7
1/23
www.st.com
1