M48Z2M1 Datasheet, PDF (1/12 Pages) STMicroelectronics – 16 Mb 2Mb x 8 ZEROPOWER SRAM

M48Z2M1
M48Z2M1Y
16 Mb (2Mb x 8) ZEROPOWER^® SRAM
INTEGRATED LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERIES
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
10 YEARS of DATA RETENTION in the
ABSENCE of POWER
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48Z2M1: 4.5V ≤ VPFD ≤ 4.75V
– M48Z2M1Y: 4.2V ≤ VPFD ≤ 4.50V
BATTERIES ARE INTERNALLY ISOLATED
UNTIL POWER IS APPLIED
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 2Mb x 8 SRAMs
36
1
PMLDIP36 (PL)
Module
Figure 1. Logic Diagram
DESCRIPTION
The M48Z2M1/2M1Y ZEROPOWER^® RAM is a
non-volatile 16,777,216 bit Static RAM organized
as 2,097,152 words by 8 bits. The device combines
two internal lithium batteries, CMOS SRAMs and a
control circuit in a plastic 36 pin DIP long Module.
The ZEROPOWER RAM replaces industry stand-
ard SRAMs. It provides the nonvolatility of PROMs
without any requirement for special write timing or
limitations on the number of writes that can be
performed.
Table 1. Signal Names
A0-A20
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
VCC
21
A0-A20
8
DQ0-DQ7
W
M48Z2M1
M48Z2M1Y
E
G
VSS
AI02048
January 1998
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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