M48Z129Y Datasheet, PDF (1/13 Pages) STMicroelectronics – 3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM

M48Z129Y
M48Z129V
3.3V/5V 1 Mbit (128Kb x8) ZEROPOWER^® SRAM
s INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, and
BATTERY
s AUTOMATIC POWER-FAIL CHIP DESELECT
AND WRITE PROTECTION
s MICROPROCESSOR POWER-ON RESET
(RESET VALID EVEN DURING BATTERY
BACK-UP MODE)
s BATTERY LOW PIN - PROVIDES WARNING
OF BATTERY END-OF-LIFE
s WRITE PROTECT VOLTAGES
(V_PFD = Power-fail Deselect Voltage):
– M48Z129Y: 4.2V ≤ V_PFD ≤ 4.5V
– M48Z129V: 2.7V ≤ V_PFD ≤ 3.0V
s CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
s 10 YEARS OF DATA RETENTION IN THE
ABSENCE OF POWER
s PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 128Kb x 8 SRAMS
s SELF CONTAINED BATTERY IN DIP
PACKAGE
Table 1. Signal Names
A0-A16
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
RST
Reset Output (Open Drain)
BL
Battery Low Output (Open
Drain)
V_CC
Supply Voltage
V_SS
Ground
32
1
PMDIP32 (PM)
Module
Figure 1. Logic Diagram
VCC
17
A0-A16
W
E
G
M48Z129Y
M48Z129V
8
DQ0-DQ7
RST
BL
VSS
AI02309
June 2000
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