M48Z128Y Datasheet, PDF (1/21 Pages) STMicroelectronics – 5.0V OR 3.3V, 1 Mbit (128 Kbit x 8) ZEROPOWER SRAM

M48Z128
M48Z128Y, M48Z128V*
5.0V OR 3.3V, 1 Mbit (128 Kbit x 8) ZEROPOWER^® SRAM
FEATURES SUMMARY
s INTEGRATED, ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, and
BATTERY
s CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
s 10 YEARS OF DATA RETENTION IN THE
ABSENCE OF POWER
s BATTERY INTERNALLY ISOLATED UNTIL
POWER IS FIRST APPLIED
s AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s WRITE PROTECT VOLTAGES:
(V_PFD = Power-fail Deselect Voltage)
– M48Z128: V_CC = 4.75 to 5.5V
4.5V ≤ V_PFD ≤ 4.75V
– M48Z128Y: V_CC = 4.5 to 5.5V
4.2V ≤ V_PFD ≤ 4.5V
– M48Z128V: V_CC = 3.0 to 3.6V
2.8V ≤ V_PFD ≤ 3.0V
s SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP WHICH
CONTAINS THE BATTERY
s SNAPHAT HOUSING (BATTERY) IS
REPLACEABLE
s PIN and FUNCTION COMPATIBLE WITH
JEDEC STANDARD 128K x 8 SRAMs
s EQUIVALENT SURFACE-MOUNT (SMT)
SOLUTION REQUIRES A 28-PIN M40Z300/W
and A STAND-ALONE 128K x8 LPSRAM
(SNAPHAT^® Top to be ordered separately)
Figure 1. 32-pin PMDIP Module
32
1
PMDIP32 (PM)
Module
* Contact Local Sales Office
October 2003
Rev. 3.4
1/21