M48Z09 Datasheet, PDF (1/13 Pages) STMicroelectronics – CMOS 8K x 8 ZEROPOWER SRAM

M48Z09
M48Z19
CMOS 8K x 8 ZEROPOWER SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
POWER-FAIL INTERRUPT
CHOICE of TWO WRITE PROTECT
VOLTAGES:
– M48Z09: 4.5V ≤ VPFD ≤ 4.75V
– M48Z19: 4.2V ≤ VPFD ≤ 4.5V
SELF CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
11 YEARS of DATA RETENTION in the
ABSENCE of POWER
PIN and FUNCTION COMPATIBLE with the
MK48Z09, 19 and JEDEC STANDARD 8K x 8
SRAMs
28
1
PCDIP28 (PC)
Battery CAPHAT
Figure 1. Logic Diagram
DESCRIPTION
The M48Z09,19 ZEROPOWER^® RAM is an 8K x 8
non-volatile static RAM which is pin and function
compatible with the MK48Z09,19.
A special 28 pin 600mil DIP CAPHAT™ package
houses the M48Z09,19 silicon with a long life lith-
ium button cell to form a highly integrated battery
backed-up memory solution.
Table 1. Signal Names
A0-A12
Address Inputs
DQ0-DQ7 Data Inputs / Outputs
INT
Power Fail Interrupt
E1
Chip Enable 1
E2
Chip Enable 2
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
VCC
13
A0-A12
8
DQ0-DQ7
W
M48Z09
E1
M48Z19
INT
E2
G
VSS
AI01184
November 1994
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