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M36W0R5020T0 Datasheet, PDF (1/26 Pages) STMicroelectronics – 32 Mbit (2Mb x16, Multiple Bank, Burst) Flash Memory and 4 Mbit SRAM, 1.8V Supply Multi-Chip Package | |||
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M36W0R5020T0
M36W0R5020B0
32 Mbit (2Mb x16, Multiple Bank, Burst) Flash Memory
and 4 Mbit SRAM, 1.8V Supply Multi-Chip Package
FEATURES SUMMARY
â MULTI-CHIP PACKAGE
â 1 die of 32 Mbit (2Mb x 16) Flash Memory
â 1 die of 4 Mbit (256Kb x16) SRAM
â SUPPLY VOLTAGE
â VDDF = VDDQ = VDDS = 1.7 to 1.95V
â LOW POWER CONSUMPTION
â ELECTRONIC SIGNATURE
â Manufacturer Code: 20h
â Device Code (Top Flash Configuration):
8814h
â Device Code (Bottom Flash
Configuration): 8815h
â PACKAGE
â Compliant with Lead-Free Soldering
Processes
â Lead-Free Versions
FLASH MEMORY
â PROGRAMMING TIME
â 8µs by Word typical for Fast Factory
Program
â Double/Quadruple Word Program option
â Enhanced Factory Program options
â MEMORY BLOCKS
â Multiple Bank Memory Array: 4 Mbit
Banks
â Parameter Blocks (Top or Bottom
location)
â SYNCHRONOUS / ASYNCHRONOUS READ
â Synchronous Burst Read mode: 66MHz
â Asynchronous/ Synchronous Page Read
mode
â Random Access: 70ns
â DUAL OPERATIONS
â Program Erase in one Bank while Read in
others
â No delay between Read and Write
operations
Figure 1. Package
FBGA
Stacked TFBGA88
(ZAQ)
â BLOCK LOCKING
â All blocks locked at Power-up
â Any combination of blocks can be locked
â WPF for Block Lock-Down
â SECURITY
â 128-bit user programmable OTP cells
â 64-bit unique device number
â COMMON FLASH INTERFACE (CFI)
â 100,000 PROGRAM/ERASE CYCLES per
BLOCK
SRAM
â ACCESS TIME: 70ns
â LOW VDDS DATA RETENTION: 1.0V
â POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
December 2004
1/26
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