M36L0T7050T0 Datasheet, PDF (1/18 Pages) STMicroelectronics – 128Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32Mbit (2M x16) PSRAM, Multi-Chip Package

M36L0T7050T0
M36L0T7050B0
128Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
32Mbit (2M x16) PSRAM, Multi-Chip Package
FEATURES SUMMARY
■ MULTI-CHIP PACKAGE
– 1 die of 128Mbit (8Mx16, Multiple Bank,
Multi-level, Burst) Flash Memory
– 1 die of 32Mbit (2Mx16) Pseudo SRAM
■ SUPPLY VOLTAGE
– V_DDF = 1.7 to 2V
– V_DDP = V_DDQ = 2.7 to 3.3V
– V_PP = 9V for fast program (12V tolerant)
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code (Top Flash Configuration)
M36L0T7050T0: 88C4h
– Device Code (Bottom Flash
Configuration) M36L0T7050B0: 88C5h
■ PACKAGE
– Compliant with Lead-Free Soldering
Processes
– Lead-Free Versions
FLASH MEMORY
■ SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode: 50MHz
– Asynchronous Page Read mode
– Random Access: 90ns
■ SYNCHRONOUS BURST READ SUSPEND
■ PROGRAMMING TIME
– 10µs typical Word program time using
Write to Buffer and Program
■ MEMORY ORGANIZATION
– Multiple Bank Memory Array: 8 Mbit
Banks
– Parameter Blocks (Top or Bottom
location)
■ DUAL OPERATIONS
– program/erase in one Bank while read in
others
– No delay between read and write
operations
■ SECURITY
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
Figure 1. Package
FBGA
TFBGA88 (ZAQ)
8 x 10mm
■ BLOCK LOCKING
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WP for Block Lock-Down
– Absolute Write Protection with V_PP = V_SS
■ COMMON FLASH INTERFACE (CFI)
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
PSRAM
■ ACCESS TIME: 70ns
■ LOW STANDBY CURRENT: 100µA
■ DEEP POWER-DOWN CURRENT: 10µA
■ BYTE CONTROL: UB_P/LB_P
■ PROGRAMMABLE PARTIAL ARRAY
■ 8 WORD PAGE ACCESS CAPABILITY: 18ns
■ POWER-DOWN MODES
– Deep Power-Down
– 4 Mbit Partial Array Refresh
– 8 Mbit Partial Array Refresh
– 16 Mbit Partial Array Refresh
December 2004
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