M28LV64 Datasheet, PDF (1/18 Pages) STMicroelectronics – 64K 8K x 8 LOW VOLTAGE PARALLEL EEPROM with SOFTWARE DATA PROTECTION

M28LV64
64K (8K x 8) LOW VOLTAGE PARALLEL EEPROM
with SOFTWARE DATA PROTECTION
FAST ACCESS TIME: 200ns
SINGLE LOW VOLTAGE OPERATION
LOW POWER CONSUMPTION
FAST WRITE CYCLE:
– 64 Bytes Page Write Operation
– Byte or Page Write Cycle: 3ms Max
ENHANCED END OF WRITE DETECTION:
– Ready/Busy Open Drain Output
(only on the M28LV64)
– Data Polling
– Toggle Bit
PAGE LOAD TIMER STATUS BIT
HIGH RELIABILITY SINGLE POLYSILICON,
CMOS TECHNOLOGY:
– Endurance >100,000 Erase/Write Cycles
– Data Retention >40 Years
JEDEC APPROVED BYTEWIDE PIN OUT
SOFTWARE DATA PROTECTION
The M28LV64 is replaced by the
M28C64-xxW
NOT FOR NEW DESIGN
28
1
PDIP28 (P)
PLCC32 (K)
28
1
SO28 (MS)
300 mils
TSOP28 (N)
8 x13.4mm
Figure 1. Logic Diagram
DESCRIPTION
The M28LV64 is an 8K x 8 low power Parallel
EEPROM fabricated with SGS-THOMSON pro-
prietary single polysilicon CMOS technology. The
device offers fast access time with low power dis-
sipation and requires a 2.7V to 3.6V power supply.
VCC
13
A0-A12
8
DQ0-DQ7
Table 1. Signal Names
A0 - A12 Address Input
DQ0 - DQ7 Data Input / Output
W
Write Enable
E
Chip Enable
G
Output Enable
RB
Ready / Busy
V_CC
Supply Voltage
VSS
Ground
W
M28LV64
E
RB *
G
VSS
AI01538B
Note: * RB function is only available on the M28LV64.
May 1997
This is information on a product still in production bu t not recommended for new de signs.
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