IMSA110 Datasheet, PDF (1/26 Pages) STMicroelectronics – IMAGE AND SIGNAL PROCESSING SUB.SYSTEM

IMSA110
IMAGE AND SIGNAL PROCESSING SUB–SYSTEM
. 1-D/2-D SOFTWARE CONFIGURABLE CON-
VOLVER/FILTER
. ON-CHIP PROGRAMMABLE LINE DELAYS (0
— 1120 STAGES)
. 8-BIT DATA AND 8.5-BIT COEFFICIENT
SLICE
. _{21 MULTIPLY-AND-ACCUMULATE STAGES}
. _{1-D (21) OR 2-D (3 x 7) CONVOLUTION WIN-}
DOW
. ON-CHIP POST PROCESSOR FOR DATA
TRANSFORMATION
. FULLY CASCADABLE IN WINDOW SIZE AND
ACCURACY
. _{20 MHZ DATA THROUGHPUT (420 MOPS)}
. _{SIGNED/UNSIGNED DATA AND COEFFI-}
CIENTS
. _{MICROPROCESSOR INTERFACE}
. _{HIGH SPEED CMOS IMPLEMENTATION}
. _{TTL COMPATIBLE}
. _{SINGLE +5V ± 10% SUPPLY}
. _{POWER DISSIPATION < 2.0 WATTS}
. _{100 PIN CERAMIC PGA}
PGA100
(Ceramic Grid Array Package)
APPLICATIONS
. _{1-D and 2-D digital convolution and correlation}
. _{Real time image processing and enhancement}
. _{Edge and feature detection}
. _{Data transformation and histogram equalisa-}
tion
. _{Computer vision and robotics}
. _{Template matching}
. _{Pulse compression}
. _{1-D or 2-D interpolation}
ORDERING INFORMATION
Part Number
Package
Clock
Speed
IMSA110-G20S PGA100 20MHz
Military/
commercial
commercial
July 1992
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