HCF4099B Datasheet, PDF (1/14 Pages) STMicroelectronics – 8 BIT ADDRESSABLE LATCH

HCF4099B
8 BIT ADDRESSABLE LATCH
s SERIAL DATA INPUT - ACTIVE PARALLEL
OUTPUT
s STORAGE REGISTER CAPABILITY -
MASTER CLEAR
s CAN FUNCTION AS DEMULTIPLEXER
s QUIESCENT CURRENT SPECIFIED UP TO
20V
s STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
s INPUT LEAKAGE CURRENT
I_I = 100nA (MAX) AT V_DD = 18V T_A = 25°C
s 100% TESTED FOR QUIESCENT CURRENT
s MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF4099B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4099B, an 8-bit addressable latch, is a
serial-input, parallel output storage register that
can perform a variety of functions. Data is input to
a particular bit in the latch when that bit is
addressed (by means of input A0, A1, A2) and
when WRITE DISABLE is at a low level. When
DIP
SOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
HCF4099BEY
HCF4099BM1
T&R
HCF4099M013TR
WRITE DISABLE is high, data entry is inhibited;
however, all 8 outputs can be continuously read
independent of WRITE DISABLE and address
inputs. A master RESET input is available, which
resets all bits to a logic "0" level when RESET and
WRITE DISABLE are at a high level. When
RESET is at a high level, and WRITE DISABLE is
at a low level, the latch acts as a 1-of-8
demultiplexer ; the bit that is addressed has an
active output which follows the data input, while all
unaddressed bits are held to a logic "0" level.
PIN CONNECTION
October 2002
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