HCF4027B_02 Datasheet, PDF (1/9 Pages) STMicroelectronics – DUAL J-K MASTER SLAVE FLIP-FLOP

HCF4027B
DUAL J-K MASTER SLAVE FLIP-FLOP
s SET RESET CAPABILITY
s STATIC FLIP-FLOP OPERATION - RETAINS
STATE INDEFINETELY WITH CLOCK LEVEL
EITHER "HIGH" OR "LOW"
s MEDIUM-SPEED OPERATION - 16MHz
(Typ. clock toggle rate at 10V)
s QUIESCENT CURRENT SPECIFIED UP TO
20V
s STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
s 5V, 10V AND 15V PARAMETRIC RATINGS
s INPUT LEAKAGE CURRENT
I_I = 100nA (MAX) AT V_DD = 18V T_A = 25°C
s 100% TESTED FOR QUIESCENT CURRENT
s MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF4027B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4027B is a single monolithic chip integrated
circuit
containing
two
identical
complementary-symmetry J-K master-slave
flip-flops. Each flip-flop has provisions for
individual J, K, Set, Reset, and Clock input
DIP
SOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
HCF4027BEY
HCF4027BM1
T&R
HCF4027M013TR
signals. Buffered Q and Q signals are provided as
outputs. This input-output arrangement provides
for compatible operation with the HCF4013B dual
D type flip-flop.
This device is useful in performing control,
register, and toggle functions. Logic levels present
at the J and K inputs, along with internal
self-steering, control the state of each flip-flop;
changes in the flip-flop state are synchronous with
the positive-going transition of the clock pulse. Set
and Reset functions are independent of the clock
and are initiated when a high level signal is
present at either the Set or Reset input.
PIN CONNECTION
September 2002
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