AN592 Datasheet, PDF (1/5 Pages) STMicroelectronics – PLL generation using ST62 auto-reload timer

AN592
Application note
PLL generation using ST62 auto-reload timer
INTRODUCTION
This note describes how to generate a digital signal locked in phase and frequency (PLL) with a
calibrated delay starting from an active edge on the Auto-reload timer input pin.
Auto-reload timer description
This timer is an 8 bit timer/counter with prescaler. It includes auto-reload PWM, capture and
compare capability with one input and one output pins. It can be controlled by the following reg-
isters (8 bit):
- ^{Mode Control Register (MC)}
- ^{Status registers (SC0, SC1)}
- ^{Load register (LR)}
- ^{Incremental counter register (TC)}
- ^{Compare register (CP)}
- ^{Reload/Capture register (RC)}
It can also wake-up the MCU from wait mode and exit from stop mode if an external event is
present on the input pin. The prescaler ratio can be programmed to choose the timer input fre-
quency F_IN (see Table 1).
Example:
The TIMIN input receives a 15 kHz digital signal. We want to generate a phase-locked 15 kHz
digital signal with a falling edge delayed 19μs from the input rising edge, and a duty cycle of
75%. The CPU quartz frequency is 8 MHz.
Figure 1. Auto-reload Timer Block Diagram
June 2008
Rev 2
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