AN4441 Datasheet, PDF (1/5 Pages) STMicroelectronics – Start time of the RHFLVDS32A receiver

AN4441
Application note
Start time of the RHFLVDS32A receiver
Jean-Louis Bernet
Introduction
This application note describes the delay it is necessary to wait before data become available at the
receiver output of the RHFLVDS32A. To explain this example, Figure 1 shows a full data link
transmission schematic where the RHFLVDS31A and RHFLVDS32A devices are implemented in cold
spare mode.
Figure 1: Cold spare, full data link implementation
1. Most of the TL lengths are balanced, both for the RHFLVDS31A_2 and RHFLVDS32A_2 data
link (TL2 and TL3) and the measurement utilities (TL4, TL5, and TL6).
2. The length of TL6 simulates a replica of the global delay introduced by the setup (TL4 length
compensation).
3. SRC1 is a continuous high speed data source.
4. SRC2 performs the enable control of the RHFLVDS32A_2 and RHFLVDS32A_1 receivers.
5. Only \G should be considered as the active control line of the RHFLVDS32A_1.
February 2014
DocID025920 Rev 1
1/5
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