AN394 Datasheet, PDF (1/10 Pages) STMicroelectronics – Within STMicroelectronics

AN394
®
APPLICATION NOTE
MICROWIRE EEPROM COMMON I/O OPERATION
Within STMicroelectronics’ broad spectrum of different types of serial access EEPROM product, the MI-
CROWIRE® family is based on a 4-wire interface. The four lines consist of: the Clock Input (C), the Chip
Select Input (S), the Serial Data Input (D), and the Serial Data Output (Q).
Some microprocessor chips, such as ST’s microcontroller series, include an on-chip Serial Peripheral In-
terface (SPI). The MICROWIRE interface is ideally suited to use with these devices. However, the MICRO-
WIRE EEPROM devices can also be used with any general purpose microcontroller, provided that care is
taken not to allow signal conflicts to result. This document discusses how to avoid such conflicts when
tying the D and Q lines together as a single bus.
While commands, addresses or data are being shifted into the D serial input of the EEPROM device, the
Q output is held in the high impedance state. It should be possible, therefore, to tie the D and Q pins to-
gether to provide a common D/Q bus, as depicted in Figure 1. The device can, indeed, operate correctly
in this configuration, provided that appropriate design rules are followed.
The potentially troublesome situations are during commands which activate the Q output (such as
READ,WRITE, ERASE, WRAL and ERAL). This document considers these cases, and recommends the
most conservative solution to each problem. In order to provide the designer with a safe design guide, all
calculations are based on worst case values, as found in the data sheets for these EEPROM devices.
Figure 1. Typical Application of the Common-D/Q Approach
Data In
Driver Enable
(active low)
D Driver
Common D/Q Bus
EEPROM Device
D
Q
Data Out
Q Receiver
CS
Clock In
Chip Select In
Ai02419
READ INSTRUCTION
The D driver and the Q receiver, in Figure 1, can be discrete logic, or part of a microcontroller I/O port, or
any equivalent circuitry. The READ command and its address bits are clocked into the chip, through the
D pin, on the rising edges of the C clock. Each bit must be kept valid for a minimum hold time (tDVCH) as
specified in the data sheet for the memory device. The device holds the Q pin in the high impedance state
during most of the input operation. However, as Figure 2 shows, the Q pin is taken out of this state at the
June 1998
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