AN1471 Datasheet, PDF (1/4 Pages) STMicroelectronics – This application note describes

AN1471
Application note
What happens to the M24xxx I²C EEPROM
if the I²C bus communication is stopped?
This application note describes what can be attempted to set an M24xxx memory back to a
known state if it has been suddenly stopped before completion of the current I²C instruction.
The method presented here will work regardless of whether the device was stopped during
an incoming or an outgoing byte transfer. It is used to resynchronize the memory device
whenever an undefined state has been detected on the I²C bus.
1
Resynchronizing the M24xxx’s internal logic
If the bus Master (the microcontroller or processor) or other components on the I²C bus have
failed, with clock and data lines being improperly driven, the internal state of the M24xxx
might reach an unknown state. The M24xxx internal logic must be resynchronized. The
analysis of this situation can be structured under the following sub-headings:
● The interrupted transmission was an incoming data byte
● The interrupted transmission was an outgoing data byte (during a READ instruction)
1.1
Caution:
The interrupted transmission was an incoming data byte
Issuing a Stop condition is sufficient to abort the transmission and place the device in the
Standby mode. However, if the last transmitted instruction was a WRITE, the Stop condition
is also able to start the internal Write cycle (if the Stop condition occurs after the 9th clock
cycle of each data byte). It is therefore risky to send a single Stop condition.
It is recommended, instead, to issue a Start condition first, followed by a Stop condition. The
Start condition aborts the transmission, and leaves the M24xxx waiting for a device select
byte; the Stop condition then sets the M24xxx in standby mode.
Resynchronization does not modify the internal address counter.
In order to define the internal address counter value, the next instruction must be either a
Byte Random Read, a Sequential Random Read or a Write (because the current Read or
Sequential Read instruction does not modify the internal address counter).
October 2009
Doc ID 8335 Rev 4
1/4
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