74V1G80 Datasheet, PDF (1/10 Pages) STMicroelectronics – SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP

74V1G80
SINGLE POSITIVE EDGE TRIGGERED
D-TYPE FLIP-FLOP
s HIGH SPEED:
f_MAX = 180MHz (TYP.) at V_CC = 5V
s LOW POWER DISSIPATION:
I_CC = 1µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28% V_CC (MIN.)
s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 8mA (MIN) at V_CC = 4.5V
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2V to 5.5V
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V1G80 is an advanced high-speed CMOS
SINGLE POSITIVE EDGE TRIGGERED D-TYPE
FLIP-FLOP WITH INVERTED OUTPUT
fabricated with sub-micron silicon gate and
double-layer metal wiring C²MOS technology. it is
designed to operate from 2V to 5.5V, making this
device ideal for portable applications.
This D-Type flip-flop is controlled by a clock input
(CK). On the positive transition of the clock, the Q
output will be set to the logic inverted state that
was setup at the D input.
SOT23-5L
SOT323-5L
ORDER CODES
PACKAGE
SOT23-5L
SOT323-5L
T&R
74V1G80STR
74V1G80CTR
Following the hold time interval, data at the D input
can be changed without affecting the level at the
output. Power down protection is provided on
input and 0 to 7V can be accepted on input with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
It’s available in the commercial temperature
range. All inputs and output are equipped with
protection circuits against static discharge, giving
them ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
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