74V1G125_04 Datasheet, PDF (1/10 Pages) STMicroelectronics – SINGLE BUS BUFFER (3-STATE)

74V1G125
SINGLE BUS BUFFER (3-STATE)
s HIGH SPEED: t_PD = 3.8ns (TYP.) at V_CC = 5V
s LOW POWER DISSIPATION:
I_CC = 1µA (MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28% V_CC (MIN.)
s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 8mA (MIN) at V_CC = 4.5V
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2V to 5.5V
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V1G125 is an advanced high-speed CMOS
SINGLE BUS BUFFER fabricated with sub-micron
silicon gate and double-layer metal wiring C²MOS
technology.
3-STATE control input G has to be set HIGH to
place the output into the high impedance state.
SOT23-5L
SOT323-5L
ORDER CODES
PACKAGE
SOT23-5L
SOT323-5L
T&R
74V1G125STR
74V1G125CTR
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2004
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