74LX1G132 Datasheet, PDF (1/11 Pages) STMicroelectronics – SINGLE 2-INPUT SCHMITT NAND GATE

74LX1G132
SINGLE 2-INPUT SCHMITT NAND GATE
s 5V TOLERANT INPUTS
s HIGH SPEED: t_PD = 5.5ns (MAX.) at V_CC = 3V
s LOW POWER DISSIPATION:
I_CC = 1µA (MAX.) at T_A = 25°C
s TYPICAL HYSTERESIS: V_h=1V at V_CC=4.5V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 24mA (MIN) at V_CC = 3V
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 1.65V to 5.5V
(1.2V Data Retention)
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LX1G132 is a low voltage CMOS SINGLE
2-INPUT NAND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C²MOS
technology.
The internal circuit is composed of 3 stages
including buffer output, which provide high noise
immunity and stable output.
SOT23-5L
SOT323-5L
ORDER CODES
PACKAGE
SOT23-5L
SOT323-5L
T&R
74LX1G132STR
74LX1G132CTR
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
This together with its schmitt trigger function
allows it to be used on line receivers with slow
rise/fall input signals.
All inputs and outputs are equipped with
protection circuits against static discharge.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2004
1/11