74LX1G125 Datasheet, PDF (1/13 Pages) STMicroelectronics – SINGLE BUS BUFFER (3-STATE)

74LX1G125
SINGLE BUS BUFFER (3-STATE)
s 5V TOLERANT INPUTS
s HIGH SPEED: t_PD = 4.7ns (MAX.) at V_CC = 3V
s LOW POWER DISSIPATION:
I_CC = 1µA (MAX.) at T_A = 25°C
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 24mA (MIN) at V_CC = 3V
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s WIDE OPERATING VOLTAGE RANGE:
V_CC(OPR) = 1.65V to 5.5V
(1.2V Data Retention)
s LATCH-UP PERFORMANCE EXCEED
300mA
s RoHS FLIP-CHIP AND SOT PACKAGES
DESCRIPTION
The 74LX1G125 is a low voltage CMOS SINGLE
BUS BUFFER fabricated with sub-micron silicon
gate and double-layer metal wiring C²MOS
technology.
3-STATE control input G has to be set HIGH to
place the output into the high impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V or lower power supply
systems. The sub-micron CMOS technology used
SOT23-5L
SOT323-5L
Flip-Chip5
(Max dim = 1.3x1.3mm)
ORDER CODES
PACKAGE
SOT23-5L
SOT323-5L
Flip-Chip5
T&R
74LX1G125STR
74LX1G125CTR
74LX1G125BJR
allow ultra low power consumption and guarantee
optimized operations between 2.8V and 1.8V
system, as Smart Phone, Digital Still Camera,
PDA, Notebook, or each other battery powered
equipment.
All inputs and outputs are equipped with
protection circuits against ESD discharge.
PIN CONNECTION AND IEC LOGIC SYMBOLS (top view for SOT, top through view for Flip-Chip)
April 2004
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