74LVXC4245 Datasheet, PDF (1/11 Pages) Fairchild Semiconductor – 8-Bit Dual Supply Configurable Voltage Interface Transceiver with 3-STATE Outputs

74LVXC4245
OCTAL DUAL SUPPLY BUS TRANSCEIVER
s HIGH SPEED:
t_PD = 6.5ns (MAX.) at
V_CCA = 5.0V, V_CCB = 5.0V
s LOW POWER DISSIPATION:
I_CCA = I_CCB = 5µA(MAX.) at T_A=25°C
s LOW NOISE: V_OLP =0.3V (TYP.) at
V_CCA=5.0V V_CCB =3.3V
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 24mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CCA(OPR) = 4.5V to 5.5V (1.2V Data Retention)
V_CCB(OPR) = 2.7V to 5.5V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES C4245
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVXC4245 is a dual supply 8 bit
configurable low voltage CMOS OCTAL BUS
TRANSCEIVER fabricated with sub-micron silicon
gate and double-layer metal wiring C²MOS
technology. Designed for use as an interface
between a 5V bus and a 3.3V to 5V bus in a mixed
5V/3.3V supply systems, it achieves high speed
operation while maintaining the CMOS low power
dissipation.
PIN CONNECTION AND IEC LOGIC SYMBOLS
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
SOP
TSSOP
74LVXC4245M
T&R
74LVXC4245MTR
74LVXC4245TTR
This IC is intended for two-way asynchronous
communication between data buses and the
direction of data transmission is determined by
DIR input. The enable input G can be used to
disable the device so that the buses are effectively
isolated.
The A-port interfaces with the 5V bus, the B-port
with the 3.3V to 5V bus.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
July 2001
1/11