74LVX27_04 Datasheet, PDF (1/11 Pages) STMicroelectronics – LOW VOLTAGE CMOS TRIPLE 3-INPUT NOR GATE WITH 5V TOLERANT INPUTS

74LVX27
LOW VOLTAGE CMOS TRIPLE 3-INPUT NOR GATE
WITH 5V TOLERANT INPUTS
s HIGH SPEED:
t_PD = 4.1ns (TYP.) at V_CC = 3.3V
s 5V TOLERANT INPUTS
s INPUT VOLTAGE LEVEL:
V_IL=0.8V, V_IH=2V at V_CC=3V
s LOW POWER DISSIPATION:
I_CC = 2 µA (MAX.) at T_A=25°C
s LOW NOISE:
V_OLP = 0.3V (TYP.) at V_CC = 3.3V
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 27
s IMPROVED LATCH-UP IMMUNITY
s POWER DOWN PROTECTION ON INPUTS
DESCRIPTION
The 74LVX27 is a low voltage CMOS TRIPLE
3-INPUT NOR GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C²MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVX27MTR
74LVX27TTR
The internal circuit is composed of 3 stages
including buffer output, which provides high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
August 2004
Rev. 3
1/11