74LVX273 Datasheet, PDF (1/12 Pages) Fairchild Semiconductor – Low Voltage Octal D-Type Flip-Flop

74LVX273
LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP
WITH CLEAR (5V TOLERANT INPUTS)
s HIGH SPEED:
f_MAX = 150 MHz (TYP.) at V_CC = 3.3V
s 5V TOLERANT INPUTS
s POWER-DOWN PROTECTION ON INPUTS
s INPUT VOLTAGE LEVEL:
V_IL = 0.8V, V_IH = 2V at V_CC =3V
s LOW POWER DISSIPATION:
I_CC = 4 µA (MAX.) at T_A=25°C
s LOW NOISE:
V_OLP = 0.3V (TYP.) at V_CC =3.3V
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4 mA (MIN) at V_CC =3V
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX273 is a low voltage CMOS OCTAL
D-TYPE FLIP-FLOP WITH CLEAR fabricated with
sub-micron silicon gate and double-layer metal
wiring C²MOS technology. It is ideal for low
power, battery operated and low noise 3.3V
applications.
Information signals applied to D inputs are
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVX273MTR
74LVX273TTR
transferred to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independently of the other inputs.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
August 2004
Rev. 3
1/12