74LVX139 Datasheet, PDF (1/12 Pages) STMicroelectronics – LOW VOLTAGE CMOS DUAL 2 TO 4 DECODER/DEMULTIPLEXER

74LVX139
LOW VOLTAGE CMOS
DUAL 2 TO 4 DECODER/DEMULTIPLEXER
s HIGH SPEED :
t_PD = 6.0ns (TYP.) at V_CC = 3.3V
s 5V TOLERANT INPUTS
s INPUT VOLTAGE LEVEL :
V_IL=0.8V, V_IH=2V at V_CC=3V
s LOW POWER DISSIPATION:
I_CC = 2 µA (MAX.) at T_A=25°C
s LOW NOISE:
V_OLP = 0.3V (TYP.) at V_CC = 3.3V
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 139
s IMPROVED LATCH-UP IMMUNITY
s POWER DOWN PROTECTION ON INPUTS
DESCRIPTION
The 74LVX139 is a low voltage CMOS DUAL 2
TO 4 DECODER/DEMULTIPLEXER fabricated
with sub-micron silicon gate and double-layer
metal wiring C²MOS technology. It is ideal for low
power, battery operated and low noise 3.3V
applications.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVX139MTR
74LVX139TTR
The active low enable input can be used for gating
or as a data input for demultiplexing applications.
While the enable input is held high, all four outputs
are high independently of the other inputs.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
August 2004
Rev. 2
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