74LVX08 Datasheet, PDF (1/8 Pages) Fairchild Semiconductor – Low Voltage Quad 2-Input AND Gate

74LVX08
LOW VOLTAGE CMOS QUAD 2-INPUT AND GATE
WITH 5V TOLERANT INPUTS
s HIGH SPEED :
t_PD = 4.8ns (TYP.) at V_CC = 3.3V
s 5V TOLERANT INPUTS
s INPUT VOLTAGE LEVEL :
V_IL=0.8V, V_IH=2V AT V_CC=3V
s LOW POWER DISSIPATION:
I_CC = 2 µA (MAX.) at T_A=25°C
s LOW NOISE:
V_OLP = 0.3V (TYP.) at V_CC = 3.3V
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 08
s IMPROVED LATCH-UP IMMUNITY
s POWER DOWN PROTECTION ON INPUTS
DESCRIPTION
The 74LVX08 is a low voltage CMOS QUAD
2-INPUT AND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C²MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LVX08M
T&R
74LVX08MTR
74LVX08TTR
The internal circuit is composed of 2 stages
including buffer output, which provides high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption. All inputs
and outputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
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