74LVTH16244 Datasheet, PDF(1/13 Page) STMicroelectronics – LOW VOLTAGE BICMOS 16 BIT BUS BUFFER WITH BUS HOLD AND POWER UP 3-STATE

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74LVTH16244 Datasheet, PDF (1/13 Pages) STMicroelectronics – LOW VOLTAGE BICMOS 16 BIT BUS BUFFER WITH BUS HOLD AND POWER UP 3-STATE

74LVTH16244

LOW VOLTAGE BICMOS 16 BIT BUS BUFFER

WITH BUS HOLD AND POWER UP 3-STATE

s HIGH SPEED:

tPD = 3.2ns (MAX.) at TA = 85Â°C VCC = 3.0V

s LOW POWER DISSIPATION HIGH LEVEL

OUTPUT: ICC = 190ÂµA (MAX.) at TA = 85Â°C

s OUTPUT IMPEDANCE:

|IOH| = 32mA, IOL = 64mA (MIN at VCC = 3.0V)

|IOH| = 8mA, IOL = 24mA (MIN at VCC = 2.7V)

s BALANCED PROPAGATION DELAYS:

tPLH â tPHL

s POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

s COMPATIBLE WITH TTL OUTPUTS:

VIH = 2V (MIN),VIL = 0.8V(MAX) at

VCC = 2.7 to 3.6V

s POWER-UP/DOWN 3-STATE: IOZPU = 100ÂµA

MAX at VCC = 0V to 1.5V, VCC = 1.5V to 0V, TA

= 85Â°C

s BUS HOLD PROVIDED ON DATA INPUTS

s OPERATING VOLTAGE RANGE:

VCC(OPR) = 2.7V to 3.6V

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES H16244

s LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

DESCRIPTION

The 74LVTH16244 is a low voltage BiCMOS 16

BIT BUS BUFFER (NON-INVERTED) fabricated

with sub-micron silicon gate and five-layer metal

wiring BiCMOS technology. It is ideal and full

specified for hot-insertion and high speed 3.3V ap-

plications; the power-up/down 3-state circuitry

places the outputs in the high impedance state

during power-up/down, which prevents driver con-

flict. This function is guaranteed when VCC is be-

tween 0 and 1.5V. It can be interfaced to 3.3V sig-

nal environment for both inputs and outputs. Any

nG output control governs four BUS BUFFERS.

Output Enable input (nG) tied together gives full

16-bit operation. When nG is LOW, the outputs

are on. When nG is HIGH, the output are in high

impedance state effectively isolated. Bus hold on

data inputs is provided in order to eliminate the

need for external pull-up or pull-down resistors.

All inputs and outputs are equipped with protec-

tion circuits against static discharge, giving them

ESD immunity and transient excess voltage.

February 2004

TSSOP

ORDER CODES

PACKAGE

TSSOP48

TFBGA54

LOGIC DIAGRAM

TFBGA

T&R

74LVTH16244TTR

74LVTH16244LBR

1/13

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