74LVQ86_04 Datasheet, PDF (1/11 Pages) STMicroelectronics – QUAD EXCLUSIVE OR GATE

74LVQ86
QUAD EXCLUSIVE OR GATE
s HIGH SPEED:
t_PD = 5.5ns (TYP.) at V_CC = 3.3 V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
I_CC = 2µA (MAX.) at T_A=25°C
s LOW NOISE:
V_OLP = 0.3V (TYP.) at V_CC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 12mA (MIN) at V_CC = 3.0 V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 86
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ86 is a low voltage CMOS QUAD
EXCLUSIVE OR GATE fabricated with
sub-micron silicon gate and double-layer metal
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ86MTR
74LVQ86TTR
wiring C²MOS technology. It is ideal for low power
and low noise 3.3V applications.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 5
1/11