74LVQ574_04 Datasheet, PDF (1/13 Pages) STMicroelectronics – OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUTS NON INVERTING

74LVQ574
OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUTS NON INVERTING
s HIGH SPEED:
f_MAX = 180 MHz (TYP.) at V_CC = 3.3V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
I_CC = 4 µA (MAX.) at T_A=25°C
s LOW NOISE:
V_OLP = 0.5V (TYP.) at V_CC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 12mA (MIN) at V_CC = 3.0V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ574 is a low voltage CMOS OCTAL
D-TYPE FLIP-FLOP with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C²MOS
technology. It is ideal for low power and low noise
3.3V applications.
These 8 bit D-Type Flip-Flops are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ574MTR
74LVQ574TTR
outputs will be set to the logic that were setup at
the D inputs. While the (OE) input is low, the 8
outputs will be in a normal logic state (high or low
logic level) and while high level the outputs will be
in a high impedance state.
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off. In order to enhance PC
board layout, the 74LVQ574 offers a pinout having
inputs and outputs on opposite side of the
package. All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 5
1/13