74LVQ373_04 Datasheet, PDF (1/13 Pages) STMicroelectronics – LOW VOLTAGE CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING

74LVQ373
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS NON INVERTING
s HIGH SPEED:
t_PD = 5.8 ns (TYP.) at V_CC = 3.3 V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
I_CC = 4 µA (MAX.) at T_A=25°C
s LOW NOISE:
V_OLP = 0.4V (TYP.) at V_CC = 3.3V
s 75Ω TRANSMISSION LINE OUTPUT DRIVE
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 12mA (MIN) at V_CC = 3.0 V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ373 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C²MOS
technology. It is ideal for low power and low noise
3.3V applications.
These 8 bit D-Type latch are controlled by a latch
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ373MTR
74LVQ373TTR
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 5
1/13