74LVQ299 Datasheet, PDF (1/15 Pages) STMicroelectronics – 8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR

74LVQ299
8 BIT PIPO SHIFT REGISTER
WITH ASYNCHRONOUS CLEAR
s HIGH SPEED:
t_PD = 8.3 ns (TYP.) at V_CC = 3.3 V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
I_CC = 4 µA (MAX.) at T_A=25°C
s LOW NOISE:
V_OLP = 0.5V (TYP.) at V_CC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 12mA (MIN) at V_CC = 3.0 V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 299
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ299 is a low voltage CMOS 8 BIT
PIPO SHIFT REGISTER (3-STATE) fabricated
with sub-micron silicon gate and double-layer
metal wiring C²MOS technology. It is ideal for low
power and low noise 3.3V applications.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ299MTR
74LVQ299TTR
These devices have four modes (HOLD, SHIFT
LEFT, SHIFT RIGHT and LOAD DATA). Each
mode is chosen by two function select inputs (S0,
S1) as shown in the Truth Table.
When one or both enable inputs, (G1, G2) are
high, the eight input/output terminals are in the
high impedance state; however sequential
operation or clearing of the register is not affected.
Clear function is asynchronous to clock.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 2
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