74LVQ273_04 Datasheet, PDF (1/13 Pages) STMicroelectronics – OCTAL D-TYPE FLIP FLOP WITH CLEAR

74LVQ273
OCTAL D-TYPE FLIP FLOP WITH CLEAR
s HIGH SPEED:
f_MAX = 150 MHz (TYP.) at V_CC = 3.3 V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
I_CC = 4 µA (MAX.) at T_A=25°C
s LOW NOISE:
V_OLP = 0.4V (TYP.) at V_CC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 12mA (MIN) at V_CC = 3.0 V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ273 is a low voltage CMOS OCTAL
D-TYPE FLIP FLOP WITH CLEAR fabricated with
sub-micron silicon gate and double-layer metal
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ273MTR
74LVQ273TTR
wiring C²MOS technology. It is ideal for low power
and low noise 3.3V applications.
Information signals applied to D inputs are
transferred to the Q outputs on the positive going
edge of the CLOCK pulse.
When the CLEAR input is held low, the Q outputs
are held low independently of the other inputs.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 5
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