74LVQ245_04 Datasheet, PDF (1/12 Pages) STMicroelectronics – LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER WITH (3-STATE)

74LVQ245
LOW VOLTAGE CMOS OCTAL BUS
TRANSCEIVER WITH (3-STATE)
s HIGH SPEED:
t_PD = 5.7 ns (TYP.) at V_CC = 3.3 V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
I_CC = 5 µA (MAX.) at T_A=25°C
s LOW NOISE:
V_OLP = 0.5V (TYP.) at V_CC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 12mA (MIN) at V_CC = 3.0 V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 245
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ245 is a low voltage CMOS OCTAL
BUS TRANSCEIVER (3-STATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C²MOS technology. It is ideal for low power
and low noise 3.3V applications.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ245MTR
74LVQ245TTR
This IC is intended for two-way asynchronous
communication between data buses and the
direction of data transmission is determined by
DIR input. The enable input G can be used to
disable the device so that the buses are effectively
isolated.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
All floating bus terminals during High Impedance
State must be held HIGH or LOW.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 5
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