74LVQ163 Datasheet, PDF (1/13 Pages) STMicroelectronics – SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

74LVQ163
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
s HIGH SPEED:
f_MAX = 180 MHz (TYP.) at V_CC = 3.3 V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
I_CC = 4 µA (MAX.) at T_A=25°C
s LOW NOISE:
V_OLP = 0.3V (TYP.) at V_CC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 12mA (MIN) at V_CC = 3.0 V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 163
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ163 is a low voltage CMOS
SYNCHRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C²MOS technology. It is
ideal for low power and low noise 3.3V
applications. It is a 4 bit binary counter with
Synchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
reset, parallel load, count-up and hold. Four
PIN CONNECTION AND IEC LOGIC SYMBOLS
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LVQ163M
T&R
74LVQ163MTR
74LVQ163TTR
control inputs, Master Reset (CLEAR), Parallel
Enable Input (LOAD), Count Enable Input (PE)
and Count Enable Carry Input (TE), determine the
mode of operation as shown in the Truth Table. A
LOW signal on CLEAR overrides counting and
parallel loading and allows all outputs to go LOW
on the next rising edge of CLOCK. A LOW signal
on LOAD overrides counting and allows
information on Parallel Data Qn inputs to be
loaded into the flip-flops on the next rising edge of
CLOCK. With LOAD and CLEAR, PE and TE
permit counting when both are high. Conversely, a
LOW signal on either PE and TE inhibits counting.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
July 2001
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