74LVQ14_04 Datasheet, PDF (1/11 Pages) STMicroelectronics – LOW VOLTAGE CMOS HEX SCHMITT INVERTER

74LVQ14
LOW VOLTAGE CMOS HEX SCHMITT INVERTER
s HIGH SPEED:
t_PD = 6 ns (TYP.) at V_CC = 3.3 V
s HYSTERESIS INPUT VOLTAGE:
V_H = 650mV (TYP.) at V_CC = 3.0 V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
I_CC = 2µA(MAX.) at T_A=25°C
s LOW NOISE:
V_OLP = 0.3V (TYP.) at V_CC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 12mA (MIN) at V_CC = 3.0 V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2V to 3.6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 14
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ14 is a low voltage CMOS HEX
SCHMITT INVERTER fabricated with sub-micron
silicon gate and double-layer metal wiring C²MOS
technology. It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 3 stages
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ14MTR
74LVQ14TTR
including buffer output, which enables high noise
immunity and stable output.
Pin configuration and function are the same as
those of the 74LVQ04 but the 74LVQ14 has
hysteresis between the positive and negative
input threshold typically of 650mV.
This together with its schmitt trigger function
allows it to be used on line receivers with slow
rise/fall input signals.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 5
1/11