74LVQ138 Datasheet, PDF (1/9 Pages) STMicroelectronics – 3 TO 8 LINE DECODER INVERTING

®
74LVQ138
3 TO 8 LINE DECODER (INVERTING)
s HIGH SPEED: t_PD = 5.5 ns (TYP.) at V_CC = 3.3V
s COMPATIBLE WITH TTL OUTPUT
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 ^oC
s LOW NOISE:
V_OLP = 0.2 V (TYP.) at V_CC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12 mA (MIN)
s PCI BUS LEVELS GUARANTEED AT 24mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ138 is a low voltage CMOS 3 TO 8 LINE
DECODER (INVERTING) fabricated with
sub-micron silicon gate and double-layer metal
wiring C²MOS technology.
It is ideal for low power and low noise 3.3V
applications.
M1
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ138M
74LVQ138T
If the device is enabled, 3 binary select inputs (A,
B and C) determine which one of the outputs will
go low. If enable input G1 is held low or either
G2A or G2B is held high, the decoding function is
inhibited and all the 8 outputs go high.
Three enable inputs are provided to ease
cascade connection and application of address
decoders for memory systems.
It has better speed performance at 3.3V than 5V
LSTTL family combinad with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
1/9