74LVQ125_04 Datasheet, PDF (1/12 Pages) STMicroelectronics – LOW VOLTAGE QUAD BUS BUFFERS (3-STATE)

74LVQ125
LOW VOLTAGE QUAD BUS BUFFERS (3-STATE)
s HIGH SPEED:
t_PD = 5 ns (TYP.) at V_CC = 3.3 V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
I_CC = 4 µA (MAX.) at T_A=25°C
s LOW NOISE:
V_OLP = 0.3V (TYP.) at V_CC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 12mA (MIN) at V_CC = 3.0 V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ125 is a low voltage CMOS QUAD
BUS BUFFERS fabricated with sub-micron silicon
gate and double-layer metal wiring C²MOS
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ125MTR
74LVQ125TTR
technology. It is ideal for low power and low noise
3.3V applications.
The device requires the same 3-STATE control
input G to be set high to place the output in to the
high impedance state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 5
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