74LVQ00_04 Datasheet, PDF (1/11 Pages) STMicroelectronics – LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE

74LVQ00
LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE
s HIGH SPEED:
t_PD = 5.5ns (TYP.) at V_CC = 3.3 V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
I_CC = 2µA (MAX.) at T_A=25°C
s LOW NOISE:
V_OLP = 0.3V (TYP.) at V_CC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 12mA (MIN) at V_CC = 3.0V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 00
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ00 is a low voltage CMOS QUAD
2-INPUT NAND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C²MOS
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ00MTR
74LVQ00TTR
technology. It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 5
1/11