74LVC573A Datasheet, PDF (1/13 Pages) NXP Semiconductors – Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State

74LVC573A
OCTAL D-TYPE LATCH
HIGH PERFORMANCE
s 5V TOLERANT INPUTS
s HIGH SPEED: t_PD = 6.8ns (MAX.) at V_CC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 24mA (MIN) at V_CC = 3V
s PCI BUS LEVELS GUARANTEED AT 24 mA
SOP
TSSOP
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 1.65V to 3.6V (1.2V Data
Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVC573AMTR
74LVC573ATTR
s LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
outputs will follow the data input precisely or
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LVC573A is a low voltage CMOS OCTAL
D-TYPE LATCH fabricated with sub-micron silicon
gate and double-layer metal wiring C²MOS
technology. It is ideal for 1.65 to 3.6 V_CC
operations and low power and low noise
applications.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
inversely. When the LE is taken low, the Q outputs
will be latched precisely or inversely at the logic
level of D input data. While the (OE) input is low,
the 8 outputs will be in a normal logic state (high or
low logic level) and while high level the outputs will
be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components. It has more speed performance at
3.3V than 5V AC/ACT family, combined with a
lower power consumption.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 3
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