74LVC245A_04 Datasheet, PDF (1/12 Pages) STMicroelectronics – LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER (NOT INVERTED) HIGH PERFORMANCE

74LVC245A
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER
(NOT INVERTED) HIGH PERFORMANCE
s 5V TOLERANT INPUTS
s HIGH SPEED: t_PD = 6.3ns (MAX.) at V_CC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 24mA (MIN) at V_CC = 3V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 1.65V to 3.6V (1.2V Data
Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 245
s LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LVC245A is a low voltage CMOS OCTAL
BUS TRANSCEIVER (3-STATE) fabricated with
sub-micron silicon gate and double-layer metal
wiring C²MOS technology. It is ideal for 1.65 to 3.6
V_CC operations and low power and low noise
applications.
This IC is intended for two-way asynchronous
communication between data buses and the
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVC245AMTR
74LVC245ATTR
direction of data transmission is determined by
DIR input. The enable input G can be used to
disable the device so that the buses are effectively
isolated.
It has more speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
All floating bus terminals during High Z State must
be held HIGH or LOW.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
.
Rev. 4
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