74LVC125A Datasheet, PDF (1/9 Pages) NXP Semiconductors – Quad buffer/line driver with 5-volt tolerant inputs/outputs 3-State

74LVC125A
LOW VOLTAGE CMOS QUAD BUS BUFFERS (3-STATE)
HIGH PERFORMANCE
s 5V TOLERANT INPUTS
s HIGH SPEED: t_PD = 4.8ns (MAX.) at V_CC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 24mA (MIN) at V_CC = 3V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 1.65V to 3.6V (1.2V Data
Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125
s LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LVC125A is a low voltage CMOS QUAD
BUS BUFFER fabricated with sub-micron silicon
gate and double-layer metal wiring C²MOS
technology. It is ideal for 1.65 to 3.6 V_CC
operations and low power and low noise
applications.
SOP
TSSO P
ORDER CODES
PACKAGE
TUBE
SOP
TSSOP
74LVC125AM
T&R
74LVC125AMTR
74LVC125ATTR
It can be interfaced to 5V signal environment for
inputs in mixed 3.3/5V system.
These devices require the same 3-STATE control
input G to be taken high to make the output go in
to the high impedance state.
It has more speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 2002
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