74LVC00A Datasheet, PDF (1/8 Pages) NXP Semiconductors – Quad 2-input NAND gate

74LVC00A
LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE
HIGH PERFORMANCE
s 5V TOLERANT INPUTS
s HIGH SPEED: t_PD = 4.3ns (MAX.) at V_CC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 24mA (MIN) at V_CC = 3V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 1.65V to 3.6V (1.2V Data
Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 00
s LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LVC00A is a low voltage CMOS QUAD
2-INPUT NAND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C²MOS
technology. It is ideal for 1.65 to 3.6 V_CC
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LVC00AM
T&R
74LVC00AMTR
74LVC00ATTR
operations and low power and low noise
applications.
It can be interfaced to 5V signal environment for
inputs in mixed 3.3/5V system.
It has more speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 2002
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