74LCX573_04 Datasheet, PDF (1/13 Pages) STMicroelectronics – OCTAL D-TYPE LATCH NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS

74LCX573
OCTAL D-TYPE LATCH NON-INVERTING (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
s 5V TOLERANT INPUTS AND OUTPUTS
s HIGH SPEED:
t_PD = 8.0 ns (MAX.) at V_CC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 24mA (MIN) at V_CC = 3V
s PCI BUS LEVELS GUARANTEED AT 24 mA
SOP
TSSOP
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LCX573MTR
74LCX573TTR
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
s LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCX573 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT
NON-INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C²MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input. When the LE is
taken low, the Q outputs will be latched at the logic
level of D input data. While the (OE) input is low,
the 8 outputs will be in a normal logic state (high or
low logic level) and while (OE) is in high level, the
outputs will be in a high impedance state.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
These 8 bit D-Type latch are controlled by a latch
Figure 1: Pin Connection And IEC Logic Symbols
September 2004
Rev. 5
1/13