74LCX138 Datasheet, PDF (1/12 Pages) Fairchild Semiconductor – Low Voltage 1-of-8 Decoder/Demultiplexer with 5V Tolerant Inputs

74LCX138
LOW VOLTAGE CMOS 3 TO 8 LINE DECODER (INV.)
WITH 5V TOLERANT INPUTS
s 5V TOLERANT INPUTS
s HIGH SPEED:
t_PD = 6.7ns (MAX.) at V_CC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 24mA (MIN) at V_CC = 3V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
s LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCX138 is a low voltage CMOS 3 TO 8
LINE DECODER (INVERTING) fabricated with
sub-micron silicon gate and double-layer metal
wiring C²MOS technology. It is ideal for low power
and high speed 3.3V applications; it can be
interfaced to 5V signal environment for inputs.
If the device is enabled, 3 binary select inputs (A,
B and C) determine which one of the outputs will
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LCX138MTR
74LCX138TTR
go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
Three enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
September 2004
Rev. 4
1/12