74AUP1G04 Datasheet, PDF (1/18 Pages) NXP Semiconductors – Low-power inverter

74AUP1G04
Low power single inverter gate
Features
■ High speed: t_PD = 4.3 ns (max.) at V_CC = 2.3 V
■ Power down protection on inputs and outputs
■ Balanced propagation delays:
t_PLH ≈ t_PHL
■ Operating voltage range:
V_CC (opr) = 1.2 to 3.6 V
■ Low power dissipation:
I_CC = 1 µA (max.) at T_A = 85 °C
■ Latch-up performance exceeds 300 mA (JESD
78, Class II)
■ ESD performance:
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Applications
■ Mobile phones
■ Personal digital assistants (PDAs)
DFN6L
SOT-665
Description
The 74AUP1G04 is a low voltage CMOS single
inverter gate fabricated with sub-micron silicon
gate and double-layer metal wiring C²MOS
technology. It is ideal for 1.2 to 3.6 V operations
and low power and low noise applications.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2kV ESD immunity and transient excess
voltage.
Table 1. Device summary
Order code
74AUPG04DTR
74AUPG04GTR
March 2008
Package
DFN6L (1.2 x 1 mm)
SOT-665 (1.6 x 1.6 mm)
Rev 1
Packing
Tape and reel
Tape and reel
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