74ALVCH16373 Datasheet, PDF (1/11 Pages) NXP Semiconductors – 2.5V/3.3V 16-bit D-type transparent latch 3-State

74ALVCH16373
LOW VOLTAGE CMOS 16-BITD-TYPE LATCH (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
s 3.6V TOLERANT INPUTS AND OUTPUTS
s HIGH SPEED :
t_PD = 3.6 ns (MAX.) at V_CC = 3.0 to 3.6V
t_PD = 4.5 ns (MAX.) at V_CC = 2.3 to 2.7V
t_PD = 6.5 ns (MAX.) at V_CC = 1.65V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 24mA (MIN) at V_CC = 3.0V
|I_OH| = I_OL = 18mA (MIN) at V_CC = 2.3V
|I_OH| = I_OL = 4mA (MIN) at V_CC = 1.65V
s OPERATING VOLTAGE RANGE:
V_CC(OPR) = 1.65V to 3.6V
s BUS HOLD PROVIDED ON DATA INPUTS
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16373
s LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74ALVCH16373 is a low voltage CMOS 16
BIT D-TYPE LATCH with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and five-layer metal wiring C²MOS
technology. It is ideal for low power and very high
speed 1.65 to 3.6V applications; it can be
interfaced to 3.6V signal environment for both
inputs and outputs.
These 16 bit D-TYPE latches are bite controlled
by two latch enable inputs (nLE) and two output
enable inputs (OE).
While the nLE input is held at a high level, the nQ
outputs will follow the data input precisely.
When the nLE is taken low, the nQ outputs will be
in a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.This device is designed to be
used with 3 state memory address drivers, etc.
Active bus-hold circuitry holds unused or undriven
inputs at a valid logic state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 2003
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