74ACT373_01 Datasheet, PDF (1/11 Pages) STMicroelectronics – OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED)

74ACT373
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS (NON INVERTED)
s HIGH SPEED: t_PD = 6ns (TYP.) at V_CC = 5V
s LOW POWER DISSIPATION:
I_CC = 4µA(MAX.) at T_A=25°C
s COMPATIBLE WITH TTL OUTPUTS
V_IH = 2V (MIN.), V_IL = 0.8V (MAX.)
s 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 24mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT373 is a high-speed CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C²MOS
technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
When the (LE) input is high , the Q outputs follow
the data (D) inputs . When the (LE) is taken low,
the Q outputs will be latched at the logic levels set
PIN CONNECTION AND IEC LOGIC SYMBOLS
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74ACT373B
74ACT373M
T&R
74ACT373MTR
74ACT373TTR
up at the D inputs. When the (OE) input is low, the
8 outputs will be in a normal logic state (high or
low logic level); when the (OE) input is high, the
outputs will be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
April 2001
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