74ACT280 Datasheet, PDF (1/8 Pages) STMicroelectronics – 9 BIT PARITY GENERATOR/CHECKER

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74ACT280
9 BIT PARITY GENERATOR/CHECKER
s HIGH SPEED: t_PD = 4 ns (TYP.) at V_CC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 ^oC
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN), VIL = 0.8V (MAX)
s 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 280
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The AC280 is an advanced high-speed CMOS 9
BIT PARITY GENERATOR - CHECKER
fabricated with sub-micron silicon gate and
double-layer metal wiring C²MOS technology. It is
ideal for low power applications mantaining high
speed operation similar to eqivalent Bipolar
Schottky TTL.
It is composed of nine data inputs (A to I) and
odd/even parity outputs (ΣODD and ΣEVEN). The
PIN CONNECTION AND IEC LOGIC SYMBOLS
B
M
(Plastic Package)
(Micro Package)
ORDER CODES :
74ACT280B
74ACT280M
nine data inputs control the output conditions.
When the number of high level input is odd,
ΣODD output is kept high and ΣEVEN output low.
Conservely, when the output is even, ΣEVEN
output is kept high and ΣODD low.
The IC generates either odd or even parity
making it flexible application.
The word-length capability is easily expanded by
cascading.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
December 1998
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