74ACT257_01 Datasheet, PDF (1/11 Pages) STMicroelectronics – QUAD 2 CHANNEL MULTIPLEXER (3-STATE)

74ACT257
QUAD 2 CHANNEL MULTIPLEXER (3-STATE)
s HIGH SPEED: t_PD = 5 ns (TYP.) at V_CC = 5V
s LOW POWER DISSIPATION:
I_CC = 4 µA(MAX.) at T_A=25°C
s COMPATIBLE WITH TTL OUTPUTS
V_IH = 2V (MIN.), V_IL = 0.8V (MAX.)
s 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 24mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 257
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT257 is an advanced high-speed CMOS
QUAD 2-CHANNEL MULTIPLEXER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C²MOS tecnology.
It is composed of an independent 2-channel
multiplexer with common SELECT and ENABLE
(OE)inputs. It is a non-inverting multiplexer. When
the ENABLE input is held HIGH, the outputs are
forced to a high impedance state. When the
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74ACT257B
74ACT257M
T&R
74ACT257MTR
74ACT257TTR
SELECT input is held LOW, "A" data is selected;
when SELECT input is held HIGH, "B" data is
selected.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
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