74ACT161_01 Datasheet, PDF (1/13 Pages) STMicroelectronics – SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

74ACT161
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
s HIGH SPEED:
f_MAX = 290MHz (TYP.) at V_CC = 5V
s LOW POWER DISSIPATION:
I_CC = 8µA(MAX.) at T_A=25°C
s COMPATIBLE WITH TTL OUTPUTS
V_IH = 2V (MIN.), V_IL = 0.8V (MAX.)
s 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 24mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 161
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT161 is an advanced high-speed CMOS
SYNCRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C²MOS tecnology. It is a
4 bit binary counter with Asynchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
reset, parallel load, count-up and hold. Four
control inputs, (CLEAR), (LOAD), (PE) and (TE),
determine the mode of operation as shown in the
Truth Table. A LOW signal on CLEAR overrides
counting and parallel loading and sets all outputs
on LOW state. A LOW signal on LOAD overrides
PIN CONNECTION AND IEC LOGIC SYMBOLS
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74ACT161B
74ACT161M
T&R
74ACT161MTR
74ACT161TTR
counting and allows information on Parallel Data
inputs to be loaded into the flip-flop on the next
rising edge of CLOCK. With LOAD and CLEAR
HIGH, PE and TE permit counting when both are
HIGH. Conversely, a LOW signal on either PE and
TE inhibits counting.
The CARRY OUTPUT is HIGH when TE is HIGH
and counter is in state 15.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
April 2001
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